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STP17NK40Z - STP17NK40ZFP
N-CHANNEL 400V - 0.23 - 15A TO-220/TO-220FP Zener-Protected SuperMESHTMPower MOSFET
TYPE STP17NK40Z STP17NK40ZFP
s s s s s s
VDSS 400 V 400 V
RDS(on) < 0.25 < 0.25
ID 15 A 15 A
Pw 150 W 35 W
TYPICAL RDS(on) = 0.23 EXTREMELY HIGH dv/dt CAPABILITY 100% AVALANCHE TESTED GATE CHARGE MINIMIZED VERY LOW INTRINSIC CAPACITANCES VERY GOOD MANUFACTURING REPEATIBILITY
3 1 2
TO-220
TO-220FP
DESCRIPTION The SuperMESHTM series is obtained through an extreme optimization of ST's well established stripbased PowerMESHTM layout. In addition to pushing on-resistance significantly down, special care is taken to ensure a very good dv/dt capability for the most demanding applications. Such series complements ST full range of high voltage MOSFETs including revolutionary MDmeshTM products.
INTERNAL SCHEMATIC DIAGRAM
APPLICATIONS s HIGH CURRENT, HIGH SPEED SWITCHING s IDEAL FOR OFF-LINE POWER SUPPLIES, ADAPTORS AND PFC s LIGHTING
ORDERING INFORMATION
SALES TYPE STP17NK40Z STP17NK40ZFP MARKING P17NK40Z P17NK40ZFP PACKAGE TO-220 TO-220FP PACKAGING TUBE TUBE
October 2002
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ABSOLUTE MAXIMUM RATINGS
Symbol VDS VDGR VGS ID ID IDM (l) PTOT IGS VESD(G-S) dv/dt (1) Viso Tj Tstg Parameter
STP17NK40Z
Value
STP17NK40ZFP
Unit V V V 15 (*) 9.4 (*) 60 (*) 35 0.28 A A A W W/C mA V V/ns 2500 V C C
Drain-source Voltage (VGS = 0) Drain-gate Voltage (RGS = 20 k) Gate- source Voltage Drain Current (continuous) at TC = 25C Drain Current (continuous) at TC = 100C Drain Current (pulsed) Total Dissipation at TC = 25C Derating Factor Gate-source Current (DC) Gate source ESD(HBM-C=100pF, R=1.5K) Peak Diode Recovery voltage slope Insulation Withstand Voltage (DC) Operating Junction Temperature Storage Temperature -15 9.4 60 150 1.2
400 400 30
20 4500 4.5 -55 to 150 -55 to 150
(l) Pulse width limited by safe operating area (1) I SD 15A, di/dt 200A/s, VDD V (BR)DSS, Tj T JMAX. (*) Limited only by maximum temperature allowed
THERMAL DATA
TO-220 Rthj-case Rthj-amb Tl Thermal Resistance Junction-case Max Thermal Resistance Junction-ambient Max Maximum Lead Temperature For Soldering Purpose 0.83 62.5 300 TO-220FP 3.6 C/W C/W C
AVALANCHE CHARACTERISTICS
Symbol IAR EAS Parameter Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max) Single Pulse Avalanche Energy (starting Tj = 25 C, ID = IAR, VDD = 50 V) Max Value 15 450 Unit A mJ
GATE-SOURCE ZENER DIODE
Symbol BVGSO Parameter Gate-Source Breakdown Voltage Test Conditions Igs= 1mA (Open Drain) Min. 30 Typ. Max. Unit V
PROTECTION FEATURES OF GATE-TO-SOURCE ZENER DIODES The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device's ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and cost-effective intervention to protect the device's integrity. These integrated Zener diodes thus avoid the usage of external components.
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ELECTRICAL CHARACTERISTICS (TCASE =25C UNLESS OTHERWISE SPECIFIED) ON/OFF
Symbol V(BR)DSS IDSS IGSS VGS(th) RDS(on) Parameter Drain-source Breakdown Voltage Zero Gate Voltage Drain Current (VGS = 0) Gate-body Leakage Current (VDS = 0) Gate Threshold Voltage Static Drain-source On Resistance Test Conditions ID = 1 mA, VGS = 0 VDS = Max Rating VDS = Max Rating, TC = 125 C VGS = 20 V VDS = VGS , ID = 100 A VGS = 10 V, ID = 7.5 A 3 3.75 0.23 Min. 400 1 50 10 4.5 0.25 Typ. Max. Unit V A A A V
DYNAMIC
Symbol gfs (1) Ciss Coss Crss Coss eq. (3) Parameter Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Equivalent Output Capacitance Parameter Turn-on Delay Time Rise Time Total Gate Charge Gate-Source Charge Gate-Drain Charge Test Conditions VDS =15 V, ID = 7.5 A VDS = 25 V, f = 1 MHz, VGS = 0 Min. Typ. 10.6 1900 271 63 175 Max. Unit S pF pF pF pF
VGS = 0V, VDS = 0V to 400V
SWITCHING ON
Symbol td(on) tr Qg Qgs Qgd Test Conditions VDD = 200 V, ID = 7.5 A RG = 4.7 VGS = 10 V (Resistive Load see, Figure 3) VDD = 320 V, ID = 15 A, VGS = 10 V Min. Typ. 25 23 65 13 35 Max. Unit ns ns nC nC nC
SWITCHING OFF
Symbol td(off) tf tr(Voff) tf tc Parameter Turn-off Delay Time Fall Time Off-voltage Rise Time Fall Time Cross-over Time Test Conditions VDD = 200 V, ID = 7.5 A RG = 4.7 VGS = 10 V (Resistive Load see, Figure 3) VDD = 320 V, ID = 15 A, RG = 4.7, VGS = 10 V (Inductive Load see, Figure 5) Min. Typ. 55 13 12 13 25 Max. Unit ns ns ns ns ns
SOURCE DRAIN DIODE
Symbol ISD ISDM (2) VSD (1) trr Qrr IRRM Parameter Source-drain Current Source-drain Current (pulsed) Forward On Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 15 A, VGS = 0 ISD = 15 A, di/dt = 100 A/s VDD = 100 V, Tj = 150C (see test circuit, Figure 5) 332 2650 16 Test Conditions Min. Typ. Max. 15 60 1.6 Unit A A V ns nC A
Note: 1. Pulsed: Pulse duration = 300 s, duty cycle 1.5 %. 2. Pulse width limited by safe operating area. 3. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS.
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Safe Operating Area For TO-220 Safe Operating Area For TO-220FP
Thermal Impedance For TO-220
Thermal Impedance For TO-220FP
Output Characteristics
Transfer Characteristics
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Transconductance Static Drain-source On Resistance
Gate Charge vs Gate-source Voltage
Capacitance Variations
Normalized Gate Threshold Voltage vs Temp.
Normalized On Resistance vs Temperature
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Source-drain Diode Forward Characteristics Normalized BVDSS vs Temperature
Maximum Avalanche Energy vs Temperature
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Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform
Fig. 3: Switching Times Test Circuit For Resistive Load
Fig. 4: Gate Charge test Circuit
Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times
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TO-220 MECHANICAL DATA
DIM. MIN. A C D D1 E F F1 F2 G G1 H2 L2 L4 L5 L6 L7 L9 DIA. 13.0 2.65 15.25 6.2 3.5 3.75 0.49 0.61 1.14 1.14 4.95 2.4 10.0 16.4 14.0 2.95 15.75 6.6 3.93 3.85 0.511 0.104 0.600 0.244 0.137 0.147 4.40 1.23 2.40 1.27 0.70 0.88 1.70 1.70 5.15 2.7 10.40 0.019 0.024 0.044 0.044 0.194 0.094 0.393 0.645 0.551 0.116 0.620 0.260 0.154 0.151 mm TYP. MAX. 4.60 1.32 2.72 MIN. 0.173 0.048 0.094 0.050 0.027 0.034 0.067 0.067 0.203 0.106 0.409 inch TYP. MAX. 0.181 0.051 0.107
A
C
D1
L2
D
F1
G1
E
Dia. L5 L7 L6 L4
P011C
L9
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F2
F
G
H2
STP17NK40Z - STP17NK40ZFP
TO-220FP MECHANICAL DATA
mm. MIN. 4.4 2.5 2.5 0.45 0.75 1.15 1.15 4.95 2.4 10 16 28.6 9.8 2.9 15.9 9 3 30.6 10.6 3.6 16.4 9.3 3.2 1.126 .0385 0.114 0.626 0.354 0.118 TYP MAX. 4.6 2.7 2.75 0.7 1 1.5 1.5 5.2 2.7 10.4 MIN. 0.173 0.098 0.098 0.017 0.030 0.045 0.045 0.195 0.094 0.393 0.630 1.204 0.417 0.141 0.645 0.366 0.126 inch TYP. MAX. 0.181 0.106 0.108 0.027 0.039 0.067 0.067 0.204 0.106 0.409
DIM. A B D E F F1 F2 G G1 H L2 L3 L4 L5 L6 L7 O
A
B
L3 L6 L7
F1 F
D
G1 H
F2
L2 L5
E
123
L4
G
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. (c) The ST logo is a registered trademark of STMicroelectronics (c) 2002 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. (c) http://www.st.com
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